The present invention relates to computer systems and, more particularly, to communications between computer system components. A major objective of the invention is to facilitate communications between computer system components where the components employ diverse byte-ordering conventions.
Society has been revolutionized by the rapid development of computer technology. A computer typically comprises an execution unit (e.g., one or more microprocessors), storage for programs and data (RAM, hard disk, etc.), and peripherals (displays, keyboards, modems, printers, etc.). As computers have become more powerful and affordable, the range of applications they serve has continually broadened. With this broadening base of applications has come the desirability of connecting greater numbers and a greater variety of peripherals.
Rather than use separate dedicated interfaces for each peripheral, most modern computers implement buses that allow several peripherals to communicate with a microprocessor, provided the peripherals conform to the bus form factor and protocol. Until recently, most buses were practically exclusive to a particular computer platform: e.g., Macintosh computers used a NuBus bus, while DOS-Windows computers used variants of an ISA (Industry Standard Architecture) bus. Due to hardware and software differences between buses, considerable work was required to adapt a product designed for one platform to another platform.
More recently, buses are being adopted across platforms. For example, the PCI (Peripheral Component Interface) bus is already used on Windows and Macintosh systems. In addition, Futurebus+ (IEEE P896.1), SCI (Scalable Coherent Interface), Serialbus ("Firewire", IEEE 1394), and USB (Universal Serial Bus) are expected to be cross platform. These buses promise to reduce development costs for peripheral manufacturers and system integrators, since a single item of hardware can be adapted to different platforms simply by using different software drivers.
Clouding the promise of peripherals that are interchangeable between platforms are the different byte-ordering conventions used by different microprocessors. A byte is a unit of data equal to eight bits. Most modern microprocessors deal with data in units, e.g., words, of data, that are an integer number of bytes long. Thus, 16-bit microprocessors deal with words that are two-bytes long, 32-bit microprocessors deal with four-byte words, and so on.
Byte order is an issue for a microprocessor which can address memory in sub-word-sized units. When a word-wide load is performed in a little-endian system, the byte with the lowest address is loaded into the least significant portion of a word-length register in the microprocessor. In a big-endian system, the byte with the lowest address is loaded into the most significant portion of a word-length register. Most microprocessors are either little endian or big endian. However, there are also mixed-endian processors (VAX floating point unit) and endian-selectable processors (PowerPC).
While each type of endianness has its advantages, the existence of the different types complicates communications in cross-platform environments. An analogy would be the merger of a right-hand drive country with a left-hand drive country: one can drive on either side of a road; however, switching back and forth can be problematic. Likewise, communication between, for example, a little-endian peripheral and a big-endian processor can be problematic. One typical scenario has the MacOS operating system running on a PowerPC processor that accesses little-endian peripherals over a PCI bus.
When a little-endian PCI peripheral transfers data to memory in four-byte chunks, memory stores the first byte as the least significant byte, which does not meet the expectation of a big-endian microprocessor. Presumably, the program operating the computer system can determine the endianness of the peripheral and of the processor and reorder the bytes as they are transferred. This reordering is referred to as "swizzling".
Having the microprocessor attend to this low-level task for the entire transfer can impair performance. To maximize performance, some bus-mastering peripherals take over a bus in accordance with a bus-arbitration protocol to effect a direct memory access (DMA). During a DMA transfer, the microprocessor is not in a position to swizzle the data. An alternative is to transfer the data without swizzling, and swizzle the data in memory after the transfer is complete. For transfers from memory, the swizzling can be done before the transfer. Swizzling data in memory allows the microprocessor some flexibility in scheduling the swizzling task, but still imposes a burden on the microprocessor, especially when large amounts of data are transferred.
To avoid burdening the microprocessor, it would be desirable to off-load the swizzle function to a communications bridge between memory and the bus over which the data transfer is to be made. The microprocessor could inform the bridge that a little-endian peripheral is transmitting data, but the data is to be swizzled so that it is stored in memory in a big-endian format. Once the swizzle instruction is sent, the microprocessor could attend to other matters.
This approach is not practical for the common situation in which a bus is handling transfers from plural peripherals at once. To allow practically concurrent data transfers, data is divided into small packets. Packet communications concerning different peripherals are time-multiplexed by the bus. In such a situation, the microprocessor cannot determine the source of any given packet. Thus, the microprocessor cannot make a determination of whether or not to swizzle.
If each data packet indicated the peripheral initiating its transfer, it would be possible, in principle, for the bridge to make the determination of whether or not to swizzle. However, several well-established bus protocols, e.g., PCI, fail to identify the master that initiates the data transfer. Thus, the communications bridge cannot determine the endianness of the source peripheral.
Accordingly, for the common situation in which the bus protocol does not require an initiating peripheral to be identified in a data packet, there has been no effective way to off-load the swizzle function from the microprocessor. Therefore, the swizzle function imposes a significant penalty on processor performance. What is needed is a less processor-intensive scheme for handling mixed-endian environments.